Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass-Reference-Cited by-同舟云学术

Self-Aligned Four-Terminal Planar Metal Double-Gate Low-Temperature Polycrystalline-Silicon Thin-Film Transistors for System-on-Glass

Published:2014 Issue:11 Volume:E97.C Page:1048-1054
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

HARA Akito¹,KAMO Shinya¹,SATO Tadashi²

Affiliation:

1. Tohoku Gakuin University

2. Hiroshima University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E97.C/11/E97.C_1048/_pdf

Reference58 articles.

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2. [2] A. O. Adan, K. Suzuki, H. Shibayama, and R. Miyake, “A half micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor (TFT) load,” Tech. Dig. 1990 VLSI Symp., pp.19–20, 1990.

3. [3] A. Kumar, J. K. O. Sin, C. T. Nguyen, and P. K. Ko, “Kink-free polycrystalline silicon double-gate elevated-channel thin-film transistors,” IEEE Trans. Electron. Dev., vol.45, no.12, pp.2514–2520, 1998.

4. [4] K. Makihira, K. Nakagawa, and T. Asano, “Double-gate poly-Si thin-film transistors fabricated using self-aligned technology,” Tech. Dig. 2001 AM-LCD, pp. 243–246, 2001.

5. [5] S. Zhang, R. Han, J. K. O. Sin, and M. Chan, “A novel self-aligned double-gate TFT technology,” IEEE Electron Device Lett., vol.22, no.11, pp.530–532, 2001.

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