Understanding Vmin Failures for Improved Testing of Timing Marginalities-Reference-Cited by-同舟云学术

Understanding Vmin Failures for Improved Testing of Timing Marginalities

Published:2022-09 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE International Test Conference (ITC)
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Author:

Singh Adit D.¹

Affiliation:

1. Auburn University,Department of Electrical and Computer Engineering,Auburn,AL,USA,36849

Funder

National Science Foundation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9983856/9983857/09983900.pdf?arnumber=9983900

Reference20 articles.

1. On Delay Fault Testing in Logic Circuits

2. Cell-aware Production test results from a 32-nm notebook processor

3. High sigma measurement of random threshold voltage variation in 14nm Logic FinFET technology

4. Behaviour Shockley and Sakurai Models in 7nm FinFet;mohammad;Proceedings of the IEEE International IOT Electronics and Mechatronics Conference (IEMTRONICS),0

5. Are Timing Marginalities Due to Process Variations the Cause of Silent Data Corruption?;singh;Keynote IEEE VLSI Test Symposium,0

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