SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation-Reference-Cited by-同舟云学术

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SRAM-Based Computing-in-Memory Macro With Fully Parallel One-Step Multibit Computation

Published:2022 Issue: Volume:5 Page:234-237
ISSN:2573-9603
Container-title:IEEE Solid-State Circuits Letters
language:
Short-container-title:IEEE Solid-State Circuits Lett.

Author:

Choi Edward Jongyoon¹^ORCID,Choi Injun¹^ORCID,Jeon Chanhee¹,Yun Gichan¹^ORCID,Yi Donghyeon¹,Ha Sohmyung²^ORCID,Chang Ik-Joon³^ORCID,Je Minkyu¹^ORCID

Affiliation:

1. School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea

2. Division of Engineering, New York University Abu Dhabi, Abu Dhabi, UAE

3. Department of Electronics, Kyung Hee University, Yongin, South Korea

Funder

Institute of Information Communications Technology Planning and Evaluation (IITP) Grant

Korean Government

IDEC, Korea

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/8011414/9677053/09891738.pdf?arnumber=9891738

Reference13 articles.

1. Matching Properties of Femtofarad and Sub-Femtofarad MOM Capacitors

2. Mismatch Characterization of Small Metal Fringe Capacitors

3. 16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing

4. A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation

5. 16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips

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2. Brain-inspired computing systems: a systematic literature review;The European Physical Journal B;2024-06

3. Negative capacitance FET based dual-split control 6T-SRAM cell design for energy efficient and robust computing-in memory architectures;Microelectronic Engineering;2024-05

4. SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology;2024 25th International Symposium on Quality Electronic Design (ISQED);2024-04-03

5. A reconfigurable in‐memory‐computation architecture with in‐situ update and shift capability;Electronics Letters;2024-04

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