A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation
Author:
Affiliation:
1. KAIST,Daejeon,South Korea
2. New York University Abu Dhabi,Abu Dhabi,United Arab Emirates
3. Kyung Hee University,Yongin,South Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9772767/9772730/09772821.pdf?arnumber=9772821
Reference4 articles.
1. A 64-Tile 2.4Mb In-Memory-Computing CNN Accelerator Employing Charge-Domain Compute;valavi;JSSC,2019
2. A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for Al Edge Chips;su;ISSCC,2021
3. 24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning
4. 15.3 A 351TOPS/W and 372.4GOPS Compute-in-Memory SRAM Macro in 7nm FinFET CMOS for Machine-Learning Applications
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4. A 22nm 56TOPS/W 6/8-bit Linearly-scalable R-2R Multiply-and-Accumulate Architecture with 2.2ns Latency;ESSCIRC 2023- IEEE 49th European Solid State Circuits Conference (ESSCIRC);2023-09-11
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