24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning-Reference-Cited by-同舟云学术

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24.5 A Twin-8T SRAM Computation-In-Memory Macro for Multiple-Bit CNN-Based Machine Learning

Published:2019-02 Issue: Volume: Page:
ISSN:
Container-title:2019 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Si Xin,Chen Jia-Jing,Tu Yung-Ning,Huang Wei-Hsing,Wang Jing-Hong,Chiu Yen-Cheng,Wei Wei-Chen,Wu Ssu-Yen,Sun Xiaoyu,Liu Rui,Yu Shimeng,Liu Ren-Shuo,Hsieh Chih-Cheng,Tang Kea-Tiong,Li Qiang,Chang Meng-Fan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/8656625/8662285/08662392.pdf?arnumber=8662392

Cited by 212 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. SITU: Stochastic input encoding and weight update thresholding for efficient memristive neural network in-situ training;Neurocomputing;2024-11

2. An 8b-Precison 16-Kb FDSOI 8T SRAM CIM macro based on time-domain for energy-efficient edge AI devices;Microelectronics Journal;2024-09

3. Bi-Directional and Operand-Controllable In-Memory Computing for Boolean Logic and Search Operations with Row and Column Directional SRAM (RC-SRAM);Micromachines;2024-08-22

4. SP-PIM: A Super-Pipelined Processing-In-Memory Accelerator With Local Error Prediction for Area/Energy-Efficient On-Device Learning;IEEE Journal of Solid-State Circuits;2024-08

5. A 28-nm Floating-Point Computing-in-Memory Processor Using Intensive-CIM Sparse-Digital Architecture;IEEE Journal of Solid-State Circuits;2024-08

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