SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology-Reference-Cited by-同舟云学术

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SRAM-Based Analog Compute-In-Memory Architecture Using C-2C Ladder And Signal Margin Assisted Design Methodology

Published:2024-04-03 Issue: Volume: Page:1-8
ISSN:
Container-title:2024 25th International Symposium on Quality Electronic Design (ISQED)
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Author:

Kushwaha Dinesh¹,Joshi Ashish²,Goel Abhishek¹,Joshi Rajiv V.³,Dasgupta Sudeb¹,Bulusu Anand¹

Affiliation:

1. Indian Institute of Technology,Electronics & communication Engineering Department,Roorkee,India

2. Intel Technology India Pvt. Ltd.,IP Engineering Group’s (IPG),Bengaluru,India

3. Yorktown Laboratory Upton,Thomas J. Watson Research Center,NY,USA,11973

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10528356/10528364/10528768.pdf?arnumber=10528768

Reference27 articles.

1. A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS

2. Challenges and Trends of SRAM-Based Computing-In-Memory for AI Edge Devices

3. Deep In-Memory Architectures in SRAM: An Analog Approach to Approximate Computing

4. Design Space and Memory Technology Co-exploration for In-Memory Computing Based Machine Learning Accelerators;He

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