PSI Design Solutions for High Speed Die-to-Die Interface in Chiplet Applications
Author:
Affiliation:
1. Samsung Electronics Co. Ltd.,Foundry Business Division,Hwaseong-si,South Korea
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816729.pdf?arnumber=9816729
Reference6 articles.
1. Design of 2.5D Interposer in High Bandwidth Memory and Through Silicon Via for High Speed Signal;pu;UBM DesignCon Conference,2019
2. High Performance Computing into Cloud Computing Services
3. Signal Integrity(SI) aware HBM2e/3 interposer design approach considering y-axis offset between logic and HBM die for HPC/AI/Network applications
4. PI/SI Analysis and Design Approach for HPC Platform Applications
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1. Modeling and Analysis of Heterogeneously Integrated Chiplet-to-Chiplet Communication Link in 2.5D Advanced Packaging;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28
2. Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package;2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS);2023-12-12
3. Exploiting signal skew to reduce delay uncertainty for chiplet interconnects;IEICE Electronics Express;2023-07-10
4. Optimal Channel Design for Die-to-Die Interface in Multi-die Integration Applications;2023 IEEE 73rd Electronic Components and Technology Conference (ECTC);2023-05
5. Chip Partition Heterogeneous Integration and Chip Split Heterogeneous Integration;Chiplet Design and Heterogeneous Integration Packaging;2023
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