Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package-Reference-Cited by-同舟云学术

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Signal Integrity Design and Analysis of Universal Chiplet Interconnect Express (UCIe) Channel in Silicon Interposer for Advanced Package

Published:2023-12-12 Issue: Volume: Page:1-3
ISSN:
Container-title:2023 IEEE Electrical Design of Advanced Packaging and Systems (EDAPS)
language:
Short-container-title:

Author:

Shin Taein¹,Kim Keunwoo¹,Park Hyunwook²,Sim Boogyo¹,Kim Seongguk¹,Kim Jihun¹,Choi Seonguk¹,Park Joonsang¹,Song Jinwook³,Kim Jaehyup⁴,Park Joung Won⁴,Kang Daehyun⁴,Kim Joungho¹

Affiliation:

1. Korea Advanced Institute of Science and Technology (KAIST),School of Electrical Engineering,Daejeon,South Korea

2. Missouri University of Science and Technology (MST),Department of Electrical and Computer Engineering,Rolla,MO,USA

3. Samsung Electronics,Development Team (Memory Business),Hwaseong,South Korea

4. Samsung Semiconductor Inc.,San Jose,CA,USA

Funder

Samsung

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10467193/10468066/10468369.pdf?arnumber=10468369

Reference5 articles.

1. Universal Chiplet Interconnect Express (UCIe): An Open Industry Standard for Innovations With Chiplets at Package Level

2. PSI Design Solutions for High Speed Die-to-Die Interface in Chiplet Applications

3. Modeling and Analysis of System-Level Power Supply Noise Induced Jitter (PSIJ) for 4 Gbps High Bandwidth Memory (HBM) I/O Interface

4. Signal Integrity and Computing Performance Analysis of a Processing-In-Memory of High Bandwidth Memory (PIM-HBM) Scheme

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