Optimal Channel Design for Die-to-Die Interface in Multi-die Integration Applications
Author:
Affiliation:
1. Foundry Business, Samsung Electronics, Co. Ltd.,Hwaseong-si,Gyeonggi-do,Korea,18448
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10195193/10195244/10195305.pdf?arnumber=10195305
Reference3 articles.
1. PSI Design Solutions for High Speed Die-to-Die Interface in Chiplet Applications
2. High-speed performance of silicon brridge die to die interconnects;braunisch;2011 IEEE 20th Conference on Eletrical Performance of Electronic Packaging and System,0
3. Chiplet based approach for heterogeneous processing and packageing architectures;mounce;2016 IEEE Aerospace Conference,0
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1. A Novel Switch Architecture for Multi-Die Optimization with Efficient Connections;Electronics;2024-08-13
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