Functional Demonstration of < 0.4-pJ/bit, 9.8 μm Fine-Pitch Dielet-to-Dielet Links for Advanced Packaging using Silicon Interconnect Fabric-Reference-Cited by-同舟云学术

Functional Demonstration of < 0.4-pJ/bit, 9.8 μm Fine-Pitch Dielet-to-Dielet Links for Advanced Packaging using Silicon Interconnect Fabric

Published:2022-05 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 72nd Electronic Components and Technology Conference (ECTC)
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Author:

Sahoo Krutikesh¹,Rathore Uneeb¹,Chandra Jangam Siva¹,Nguyen Tri¹,Markovic Dejan¹,Iyer Subramanian S.¹

Affiliation:

1. UCLA Center for Heterogeneous Integration and Performance Scaling (UCLA CHIPS) Electrical and Computer Engineering University of California, Los Angeles (UCLA),Los Angeles,CA

Funder

Semiconductor Research Corporation

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9816066/9816372/09816395.pdf?arnumber=9816395

Reference28 articles.

1. Study of solder bridging for the purpose of assembling three-dimensional structures

2. Warpage control of silicon interposer for 2.5D package application

3. Demonstration of a Low Latency (<20 ps) Fine-pitch (≤10 μm) Assembly on the Silicon Interconnect Fabric

4. A 16nm 785GMACs/J 784-Core Digital Signal Processor Array With a Multilayer Switch Box Interconnect, Assembled as a 2×2 Dielet with 10μm-Pitch Inter-Dielet I/O for Runtime Multi-Program Reconfiguration

5. Latency, Bandwidth and Power Benefits of the SuperCHIPS Integration Scheme

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