A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration-Reference-Cited by-同舟云学术

A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration

Published:2023-01 Issue:1 Volume:58 Page:111-123
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Nagi Sumeet Singh¹^ORCID,Rathore Uneeb¹,Sahoo Krutikesh²,Ling Tim²,Iyer Subramanian S.²^ORCID,Markovic Dejan²

Affiliation:

1. University of California at Los Angeles, Los Angeles, CA, USA

2. Department of Electrical and Computer Engineering, University of California at Los Angeles, Los Angeles, CA, USA

Funder

Defense Advanced Research Projects Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9999561/09931439.pdf?arnumber=9931439

Reference40 articles.

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3. A Survey on Coarse-Grained Reconfigurable Architectures From a Performance Perspective

4. MATRIX: A reconfigurable computing architecture with configurable instruction distribution and deployable resources;Proc IEEE Symp FPGAs Custom Comput Mach,1996

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