Author:
Bharathi M.,Shirur Yasha Jyothi M,Lahari P.L.
Cited by
12 articles.
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1. High Speed Single Precision 64-Tap FIR Filter Using Urdhva Tiryagbhyam Sutra;2024 IEEE Students Conference on Engineering and Systems (SCES);2024-06-21
2. Design and Evaluation of 32-Bit N-Tap FIR Filter for Audio Processing Applications;2024 1st International Conference on Innovative Sustainable Technologies for Energy, Mechatronics, and Smart Systems (ISTEMS);2024-04-26
3. Efficiency Evaluation of Scalable Multiply and Accumulate Architectures in DSP: A Comparative Study of LUT Based and LUT-Less Based Approaches;2024 International Conference on Intelligent and Innovative Technologies in Computing, Electrical and Electronics (IITCEE);2024-01-24
4. Design and Verification process of Combinational Adder using UVM Methodology;2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS);2023-04-19
5. FIR Filter design using Urdhva Triyagbhyam based on Truncated Wallace and Dadda Multiplier as Basic Multiplication Unit;2023 IEEE 12th International Conference on Communication Systems and Network Technologies (CSNT);2023-04-08