Design and Evaluation of 32-Bit N-Tap FIR Filter for Audio Processing Applications
Author:
Affiliation:
1. School of Engineering, Mohan Babu University erstwhile Sree Vidyanikethan Engineering College,Department of ECE,Tirupati,India
2. Sree Vidyanikethan Engineering College,Department of ECE,Tirupati,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx8/10560062/10560067/10560173.pdf?arnumber=10560173
Reference16 articles.
1. FIR Filter design using Urdhva Triyagbhyam based on Truncated Wallace and Dadda Multiplier as Basic Multiplication Unit
2. Design and Implementation of Arithmetic based FIR Filters for DSP Application
3. Design and Verification process of Combinational Adder using UVM Methodology
4. High-Speed DSP Pipelining and Retiming techniques for Distributed-Arithmetic RNS-based FIR Filter Design
5. Booth Multiplier-Based Robust Model of FIR Filters for VLSI Applications
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