Design and Verification process of Combinational Adder using UVM Methodology-Reference-Cited by-同舟云学术

Design and Verification process of Combinational Adder using UVM Methodology

Published:2023-04-19 Issue: Volume: Page:
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Container-title:2023 International Conference on Advances in Electronics, Communication, Computing and Intelligent Information Systems (ICAECIS)
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Author:

Dharani M.¹,Bharathi M.¹,Padmaja N.¹,Praveena K.¹

Affiliation:

1. Sree Vidyanikethan Engineering College,Electronic and Communication Engineering,Tirupati,Andhra Pradesh,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10169132/10169913/10170273.pdf?arnumber=10170273

Reference10 articles.

1. A Novel Realization of Multiplier Design for Signal Processing;dharani;J Pharm Negat Results,2022

2. Role of Embedded Systems in Industrial Section-By considering the Automotive Industry as an Example;ashreetha;Journal of optoelectronics laser,2022

3. Influence of Artificial Intelligence Technology on Teaching Slow Learners;dharani;International Journal of Early Childhood Special Education (INT-JECS),2022

4. An Introduction to Universal Verification Methodology for the digital design of Integrated circuits (IC’s): A Review

5. Research and implementation of an automatic simulation tool

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