Track-and-Hold Techniques for Ultra High Speed Time-Interleaved ADCs-Reference-Cited by-同舟云学术

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Track-and-Hold Techniques for Ultra High Speed Time-Interleaved ADCs

Published:2022-10-28 Issue: Volume: Page:
ISSN:
Container-title:2022 7th International Conference on Integrated Circuits and Microsystems (ICICM)
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Author:

Wang Di¹,Miao Peng¹,Li Fei¹,Yu Yahan¹,Zhang Haotian¹,Ding Ankang¹

Affiliation:

1. Institute of RF- & OE-ICs Southeast University,Nanjing,China

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10011216/10011228/10011372.pdf?arnumber=10011372

Reference10 articles.

1. A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB

2. A 32.5-GS/s two-channel time-interleaved CMOS sampler with switched-source follower based track-and-hold amplifier;ma;2014 IEEE MTT-S International Microwave Symposium (IMS2014),2014

3. High-speed highly-linear CMOS S/H circuit

4. 3.3 A 5GS/s 158.6mW 12b Passive-Sampling 8×-Interleaved Hybrid ADC with 9.4 ENOB and 160.5dB FoMS in 28nm CMOS

5. A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth

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