Author:
Sadollahy Mahmoud,Hadidi Khayrollah
Cited by
4 articles.
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1. A Design Aid Tool for Asynchronous SAR ADCs;2024 14th International Conference on Electrical Engineering (ICEENG);2024-05-21
2. A Sample and Hold Architecture with Folded Cascode Operational Amplifier using Gain Compression for Improved Linearity Implemented in 90 nm CMOS Technology;2023 26th International Conference on Computer and Information Technology (ICCIT);2023-12-13
3. Track-and-Hold Techniques for Ultra High Speed Time-Interleaved ADCs;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28
4. A new high-speed, high-resolution open-loop CMOS sample and hold;Analog Integrated Circuits and Signal Processing;2013-09-25