A 12.8 GS/s Time-Interleaved ADC With 25 GHz Effective Resolution Bandwidth and 4.6 ENOB

Author:

Duan Yida,Alon Elad

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Cited by 30 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Machine-Learning-Based Mismatch Calibration for Time-Interleaved ADCs;IEEE Transactions on Nuclear Science;2024-08

2. A comprehensive review of time skew background calibration and mitigation techniques in high‐speed time‐interleaved analog‐to‐digital converters;International Journal of Circuit Theory and Applications;2024-06-12

3. A Power-Efficient Clock Circuit and Output Serializing Technique Integrated in a 12-bit 10-GS/s ADC;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-04

4. Blind Calibration Algorithm for Time-interleaved Analog-to-Digital Conversion System;2023 International Conference on Microwave and Millimeter Wave Technology (ICMMT);2023-05-14

5. A 6.0–11.0 Gb/s Reference-Less Sub-Baud-Rate Linear CDR With Wide-Range Frequency Acquisition Technique;IEEE Transactions on Circuits and Systems II: Express Briefs;2023-02

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