A CMOS track-and-hold circuit with beyond 30 GHz input bandwidth
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/6450169/6463499/06463786.pdf?arnumber=6463786
Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献
1. Track-and-Hold Techniques for Ultra High Speed Time-Interleaved ADCs;2022 7th International Conference on Integrated Circuits and Microsystems (ICICM);2022-10-28
2. A 12-bit, 1.1-GS/s, Low-Power Flash ADC;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2022-03
3. A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS;Journal of Circuits, Systems and Computers;2020-11-20
4. A 4-Bit 1GS/s Folding Flash ADC using 45-nm CMOS Technology;Microprocessors and Microsystems;2020-11
5. Design and Characterization of a 3-bit 24-GS/s Flash ADC in 28-nm Low-Power Digital CMOS;IEEE Transactions on Microwave Theory and Techniques;2016-04
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