Linearity and Analog Performance Analysis of Double Gate Tunnel FET With Source Pocket
Author:
Affiliation:
1. National Institute of Technology,Electronics and Communication Engg. Department,Hamirpur,H.P,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9791456/9791491/09791609.pdf?arnumber=9791609
Reference21 articles.
1. Analysis of Pocket Double Gate Tunnel FET for Low Stand by Power Logic Circuits;jha;International Journal of VLSI Design & Communication Systems (VLSICS),2013
2. A Low Power Single Gate L-shaped TFET for High Frequency Application
3. Optimization of L-shaped tunneling field-effect transistor for ambipolar current suppression and Analog/RF performance enhancement
4. Performance investigation of InAs based dual electrode tunnel FET on the analog/RF platform
5. A new design approach to improve dc, analog/rf and linearity metrics of vertical tfet for rfic desig n;chauhan;Superlattices and Microstructures,2018
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