Extensive Investigation on Even-Transistor-Configuration CMOS-based SRAM

Abstract

Designing electronic devices with higher efficiency while using reduced power is a problem in the field of electronics. Digital technology utilization is increasing due to its higher speeds, lower power requirements, and stability. Accessing data requires a lot of time, so a circuit is created that will be close to the CPU to provide the information that is required. Cache memory is a type of SRAM-based faster storing device. To enhance the performance of the SRAM cell, Read Delay (RD), Write Delay (WD), read stability, write stability and power dissipation of the intended circuit should all be carefully considered while designing an efficient SRAM cell. Delay, power dissipation, and circuit stability all trade-off with one other. In this chapter, we will look at delays, average power dissipation (APD), and stability using a variety of cell ratios, pull-up ratios, and supply voltages, and compare how each of these metrics has improved. As miniaturization of post CMOS technology, technology nodes are getting smaller. Because of this, researchers have examined different typologies, ranging from 6T SRAM to 12T SRAM (even-number transistor cell) analysis. Better delays and an improved static noise margin are obtained by increasing the number of transistors per cell, although power dissipation increases as a result. This chapter covers the overall analysis for SRAM cells with 6T, 8T, 10T, and 12T transistors that vary in CR and PR as well as voltage. The circuits are created for the overall study using a 180nm technology file in the Cadence Virtuoso tool.