Implementation of Logic Gates using Charge Plasma Based Tunnel FET
Author:
Affiliation:
1. National Institute of Technology,Electronics and Communication Engineering Department,Hamirpur,India
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10127221/10127228/10127417.pdf?arnumber=10127417
Reference28 articles.
1. Implementation of Boolean Functions Using Tunnel Field-Effect Transistors
2. Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation
3. Linearity and Analog Performance Analysis of Double Gate Tunnel FET With Source Pocket
4. Junctionless Tunnel Field Effect Transistor
5. Optimization of a Pocketed Dual-Metal-Gate TFET by Means of TCAD Simulations Accounting for Quantization-Induced Bandgap Widening
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