A Suite of Division Algorithms for Posit Arithmetic

Author:

Murillo Raul1,Del Barrio Alberto A.2,Botella Guillermo2

Affiliation:

1. University of Madrid,Faculty of Physics,Dept. of Computer Architecture and Automation,Madrid,Spain,28040

2. University of Madrid,Faculty of Computer Science Complutense,Dept. of Computer Architecture and Automation,Madrid,Spain,28040

Publisher

IEEE

Cited by 4 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA;Digital Signal Processing;2024-12

2. Square Root Unit with Minimum Iterations for Posit Arithmetic;2024 IEEE 31st Symposium on Computer Arithmetic (ARITH);2024-06-10

3. Big-PERCIVAL: Exploring the Native Use of 64-Bit Posit Arithmetic in Scientific Computing;IEEE Transactions on Computers;2024-06

4. Generating Posit-Based Accelerators With High-Level Synthesis;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-10

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