A Suite of Division Algorithms for Posit Arithmetic
Author:
Affiliation:
1. University of Madrid,Faculty of Physics,Dept. of Computer Architecture and Automation,Madrid,Spain,28040
2. University of Madrid,Faculty of Computer Science Complutense,Dept. of Computer Architecture and Automation,Madrid,Spain,28040
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10265289/10265693/10265728.pdf?arnumber=10265728
Reference15 articles.
1. Computer Arithmetic Algorithms
2. A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture
3. PLAM: a Posit Logarithm-Approximate Multiplier
4. Computer Multiplication and Division Using Binary Logarithms
5. Posit Arithmetic Hardware Implementations with The Minimum Cost Divider and SquareRoot
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2. Square Root Unit with Minimum Iterations for Posit Arithmetic;2024 IEEE 31st Symposium on Computer Arithmetic (ARITH);2024-06-10
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