Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA-Reference-Cited by-同舟云学术

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Design of a novel low-latency parameterizable posit adder/subtractor using leading one predictor in FPGA

Published:2024-12 Issue: Volume:155 Page:104718
ISSN:1051-2004
Container-title:Digital Signal Processing
language:en
Short-container-title:Digital Signal Processing

Author:

Özkılbaç Bahadır^ORCID,Karacalı Tevhit

Publisher

Elsevier BV

Reference49 articles.

1. Cost-effective fixed-point hardware support for RISC-V embedded systems;Zoni;J. Syst. Architect.,2022

2. An efficient real-time accelerator for high-accuracy DNN-based optical flow estimation in FPGA;Yan;J. Syst. Architect.,2023

3. Hardware accelerator for an accurate local stereo matching algorithm using binary neural network;Ling;J. Syst. Architect.,2021

4. IEEE Std 754-2019 (Revision of IEEE 754-2008),2019

5. The End of Error: Unum Computing;Gustafson,2017

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