A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/9102708/9105359/09105517.pdf?arnumber=9105517
Cited by 11 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Square Root Unit with Minimum Iterations for Posit Arithmetic;2024 IEEE 31st Symposium on Computer Arithmetic (ARITH);2024-06-10
2. A Review of Posit Arithmetic for Energy-Efficient Computation: Methodologies, Applications, and Challenges;Design and Applications of Emerging Computer Systems;2023-08-17
3. A Suite of Division Algorithms for Posit Arithmetic;2023 IEEE 34th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2023-07
4. PLAUs: Posit Logarithmic Approximate Units to Implement Low-Cost Operations with Real Numbers;Next Generation Arithmetic;2023
5. A Low-Latency Divider Design for Embedded Processors;Sensors;2022-03-23
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