A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
Author:
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/8355238/8357004/08357056.pdf?arnumber=8357056
Cited by 5 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 12-bit 1.1GS/s Single-Channel Pipelined-SAR ADC with Adaptive Inter-stage Redundancy;2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2023-06-11
2. Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter;IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences;2023-05-01
3. VLSI Implementation of a High-Speed Pipeline A/D Converter;Role of 6G Wireless Networks in AI and Blockchain-Based Applications;2023-02-24
4. A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process;Electronics;2023-02-12
5. A generation and distribution system of clock signal source for signal acquisition system;Engineering Reports;2021-12-30
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