A 12-bit 1.1GS/s Single-Channel Pipelined-SAR ADC with Adaptive Inter-stage Redundancy
Author:
Affiliation:
1. Southern Methodist University,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10186107/10186112/10186119.pdf?arnumber=10186119
Reference6 articles.
1. A 1Gsps, 12-bit, single-channel pipelined ADC with dead-zone-degenerated ring amplifiers
2. A lOb 1.5GS/s Pipelined-SAR ADC with Background Second-Stage Common-Mode Regulation and Offset Calibration in 14nm CMOS FinFET;kull;IEEE Int Solid-State Circuits Conf (ISSCC),0
3. A 12-b 1-GS/s 61-dB SNDR Pipelined-SAR ADC With Inverter-Based Residual Amplifier and Tunable Harmonic-Injecting Cross-Coupled-Pair for Distortion Cancelation Achieving 6.3 fJ/conv-step
4. A 1MS/s to 1GS/s Ringamp-Based Pipelined ADC with Fully Dynamic Reference Regulation and Stochastic Scope-on-Chip Background Monitoring in 16nm
5. 3.2 A 7.6mW 1GS/s 60dB SNDR Single-Channel SAR-Assisted Pipelined ADC with Temperature-Compensated Dynamic Gm-R-Based Amplifier
Cited by 1 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS;IEEE Access;2024
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