A 12-b 1-GS/s 61-dB SNDR Pipelined-SAR ADC With Inverter-Based Residual Amplifier and Tunable Harmonic-Injecting Cross-Coupled-Pair for Distortion Cancelation Achieving 6.3 fJ/conv-step

Author:

Fang Liang1ORCID,Fu Tao1ORCID,Wen Xianshan1ORCID,Gui Ping1ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Southern Methodist University, Dallas, TX, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Reference10 articles.

1. A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

2. 16.1 A 13b 4 GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC;vaz;Proc IEEE Int Solid-State Circuits Conf (ISSCC),2017

3. A 9.1 ENOB 21.7 fJ/conversion-step 10b 500 MS/s single-channel pipelined SAR ADC with a current-mode fine ADC in 28nm CMOS;moon;Proc IEEE Symp VLSI Circuits (VLSIC),2017

4. 16.3 A single-channel 5.5 mW 3.3 GS/s 6b fully dynamic pipelined ADC with post-amplification residue generation;zheng;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2020

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. A PVT-Robust Open-loop Gm-Ratio ×16 Gain Residue Amplifier for >1 GS/s Pipelined ADCs;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. A 12-bit 1.1GS/s Pipelined-SAR ADC With Adaptive Inter-Stage Redundancy in 28 nm CMOS;IEEE Access;2024

3. A 12-bit 1.1GS/s Single-Channel Pipelined-SAR ADC with Adaptive Inter-stage Redundancy;2023 IEEE Radio Frequency Integrated Circuits Symposium (RFIC);2023-06-11

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