Thermal Noise Analysis of Ring Amplifier in Cyclic Analog-to-Digital Converter
Author:
Affiliation:
1. Tokyo City University
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Subject
Applied Mathematics,Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Signal Processing
Link
https://www.jstage.jst.go.jp/article/transfun/E106.A/5/E106.A_2022GCP0003/_pdf
Reference35 articles.
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3. [3] M. Ding, P. Harpe, Y.-H. Liu, B. Busze, K. Philips, and H. de Groot, “A 5.5fJ/conv-step 6.4MS/S 13b SAR ADC utilizing a redundancy-facilitated background error-detection-and-correction scheme,” 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of Technical Papers, pp.1-3, 2015, doi: 10.1109/ISSCC.2015.7063125. 10.1109/isscc.2015.7063125
4. [4] J. Lagos, N. Markulic, B. Hershberg, D. Dermit, M. Shrivas, E. Martens, and J. Craninckx, “A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-based pipelined-SAR ADC with background calibration and dynamic reference regulation in 16-nm CMOS,” IEEE Journal of Solid-State Circuits, vol.57, no.4, pp.1112-1124, April 2022, doi: 10.1109/JSSC.2021.3133829. 10.1109/jssc.2021.3133829
5. [5] L. Wei, Z. Zheng, N. Markulic, J. Lagos, E. Martens, Y. Zhu, C.-H. Chan, J. Craninckx, and R.P. Martins, “An auxiliary-channel-sharing background distortion and gain calibration achieving >8dB SFDR improvement over 4th Nyquist zone in 1GS/s ADC,” 2021 Symposium on VLSI Circuits, pp.1-2, 2021, doi: 10.23919/VLSICircuits52068.2021.9492336. 10.23919/vlsicircuits52068.2021.9492336
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