A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS-Reference-Cited by-同舟云学术

A 10.1-ENOB, 6.2-fJ/conv.-step, 500-MS/s, Ringamp-Based Pipelined-SAR ADC With Background Calibration and Dynamic Reference Regulation in 16-nm CMOS

Published:2022-04 Issue:4 Volume:57 Page:1112-1124
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Lagos Jorge¹^ORCID,Markulic Nereo¹^ORCID,Hershberg Benjamin¹^ORCID,Dermit Davide¹^ORCID,Shrivas Mithlesh¹^ORCID,Martens Ewout¹^ORCID,Craninckx Jan¹^ORCID

Affiliation:

1. IMEC, Leuven, Belgium

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9741814/09676619.pdf?arnumber=9676619

Reference34 articles.

1. A low-noise self-calibrating dynamic comparator for high-speed ADCs

2. Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures

3. A 6-Bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS

4. Analysis and Design of Regenerative Comparators for Low Offset and Noise

5. An 820?W 9 b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS;giannini;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2008

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