A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process
Author:
Affiliation:
1. School of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China
2. Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, China
3. Acela Microelectronics Co., Ltd., Suzhou 215124, China
Abstract
Funder
“Strategic Priority Research Program” of the Chinese Academy of Sciences
Publisher
MDPI AG
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Hardware and Architecture,Signal Processing,Control and Systems Engineering
Link
https://www.mdpi.com/2079-9292/12/4/924/pdf
Reference39 articles.
1. A Spectral-Correlation-Based Blind Calibration Method for Time-Interleaved ADCs;Niu;IEEE Trans. Circuits Syst. I Regul. Pap.,2020
2. A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC with Dynamic Gm-R-Based Amplifier;Jiang;IEEE J. Solid-State Circuits,2020
3. A 5-GS/s 158.6-mW 9.4-ENOB Passive-Sampling Time-Interleaved Three-Stage Pipelined-SAR ADC with Analog–Digital Corrections in 28-nm CMOS;Ramkaj;IEEE J. Solid-State Circuits,2020
4. A 12-Bit, 300-MS/s Single-Channel Pipelined-SAR ADC With an Open-Loop MDAC;Wu;IEEE J. Solid-State Circuits,2019
5. A high-frequency and high-resolution fourth-order /spl Sigma//spl Delta/ A/D converter in BiCMOS technology;Guangming;IEEE J. Solid-State Circuits,1994
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