A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity
Author:
Affiliation:
1. Institute of Microelectronics of the Chinese Academy of Sciences
2. University of Chinese Academy of Sciences
Publisher
Institute of Electronics, Information and Communications Engineers (IEICE)
Link
https://www.jstage.jst.go.jp/article/elex/advpub/0/advpub_21.20240457/_pdf
Reference31 articles.
1. [1] A. M. A. Ali, et al.: “A 14 Bit 1 GS/s RF Sampling Pipelined ADC With Background Calibration,” IEEE J. Solid-State Circuits 49 (2014) 2857 (DOI: 10.1109/JSSC.2014.2361339)
2. [2] A. M. A. Ali, et al.: “A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither,” VLSI (2016) 1 (DOI: 10.1109/VLSIC.2016.7573537)
3. [3] X. Fangyuan, et al.: “A 12-Bit 1-GS/s Pipelined ADC with a Novel Timing Strategy in 40-nm CMOS Process,” MDPI Electron. 12 (2023)
4. [4] Y.-Z. Xi, et al.: “An energy-efficient reconfigurable 18/12-bit 1 MS/s pipelined-SAR ADC,” AEU Int. J. Electron. Commun. 179 (2024) 155309 (DOI: 10.1016/j.aeue.2024.155309)
5. [5] B. Vaz, et al.: “16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC,” ISSCC (2017) 276 (DOI: 10.1109/ISSCC.2017.7870368)
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