16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC-Reference-Cited by-同舟云学术

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16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADC

Published:2017-02 Issue: Volume: Page:
ISSN:
Container-title:2017 IEEE International Solid-State Circuits Conference (ISSCC)
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Author:

Vaz Bruno,Lynam Adrian,Verbruggen Bob,Laraba Asma,Mesadri Conrado,Boumaalif Ali,Mcgrath John,Kamath Umanath,De Le Torre Ronnie,Manlapat Alvin,Breathnach Daire,Erdmann Christophe,Farley Brendan

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7866667/7870233/07870368.pdf?arnumber=7870368

Cited by 55 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 2-GS/s Time-Interleaved ADC With Embedded Background Calibrations and a Novel Reference Buffer for Reduced Inter-Channel Crosstalk;IEEE Journal of Solid-State Circuits;2024

2. An Active Track and Hold Circuit With Linearity Enhancement Technique and Its Analysis Using Volterra Series;IEEE Access;2024

3. A 12-bit 1.5-GS/s Single-Channel Pipelined SAR ADC With a Pipelined Residue Amplification Stage;IEEE Journal of Solid-State Circuits;2024

4. A Single-Channel 12-b 2-GS/s PVT-Robust Pipelined ADC With Sturdy Ring Amplifier and Time-Domain Quantizer;IEEE Journal of Solid-State Circuits;2024

5. A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity;IEICE Electronics Express;2024

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