A Trip Down Memory Lane: Reflections on the progress in memories-Reference-Cited by-同舟云学术

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A Trip Down Memory Lane: Reflections on the progress in memories

Published:2023 Issue:3 Volume:15 Page:53-61
ISSN:1943-0582
Container-title:IEEE Solid-State Circuits Magazine
language:
Short-container-title:IEEE Solid-State Circuits Mag.

Author:

Chang Tsung-Yung Jonathan¹,Hamzaoglu Fatih²^ORCID,Li Yan³,Sohn Kyomin⁴^ORCID,Wang Yih⁵,Wuu John⁶^ORCID

Affiliation:

1. TSMC Fellow leading memory IP development, TSMC, Hsinchu, Taiwan, China

2. Technology Development Group, Intel Corporation, Hillsboro, OR, USA

3. Memory Technology, Western Digital, Milpitas, CA, USA

4. Samsung Electronics, Hwaseong, Gyeonggi-do, South Korea

5. TSMC in Hsinchu, Taiwan, China

6. Design Engineer, AMD, Fort Collins, CO, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4563670/10224560/10224514.pdf?arnumber=10224514

Reference22 articles.

1. An 8-Gb GDDR6X DRAM Achieving 22 Gb/s/pin With Single-Ended PAM-4 Signaling

2. A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

3. 25.4 A 20nm 6GB Function-In-Memory DRAM, Based on HBM2 with a 1.2TFLOPS Programmable Computing Unit Using Bank-Level Parallelism, for Machine Learning Applications

4. A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

5. A 28nm HKMG super low power embedded NVM technology based on ferroelectric FETs

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