A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process-Reference-Cited by-同舟云学术

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process

Published:2022-02-20 Issue: Volume: Page:
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Container-title:2022 IEEE International Solid- State Circuits Conference (ISSCC)
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Author:

Kim Dae-Hyun¹,Song Byungkyu¹,Ahn Hyun-a¹,Ko Woongjoon¹,Do Sunggeun¹,Cho Seokjin¹,Kim Kihan¹,Oh Seung-Hoon¹,Joo Hye-Yoon¹,Park Geuntae¹,Jang Jin-Hun¹,Kim Yong-Hun¹,Lee Donghun¹,Jung Jaehoon¹,Kwon Yongmin¹,Kim Youngjae¹,Jung Jaewoo¹,O Seongil¹,Lee Seoulmin¹,Lim Jaeseong¹,Son Junho¹,Min Jisu¹,Do Haebin¹,Yoon Jaejun¹,Hwang Isak¹,Park Jinsol¹,Shim Hong¹,Yoon Seryeong¹,Choi Dongyeong¹,Lee Jihoon¹,Woo Soohan¹,Hong Eunki¹,Choi Junha¹,Kim Jae-Sung¹,Han Sangkeun¹,Bang Jongmin¹,Park Bokgue¹,Kim Janghoo¹,Choi Seouk-Kyu¹,Han Gong-Heum¹,Sung Yoo-Chang¹,Bae Won-Il¹,Lim Jeong-Don¹,Lee Seungjae¹,Yoo Changsik¹,Hwang Sang Joon¹,Lee Jooyoung¹

Affiliation:

1. Samsung Electronics,Hwaseong,Korea

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9731529/9731102/09731537.pdf?arnumber=9731537

Reference5 articles.

1. A 16Gb 18Gb/S/pin GDDR6 DRAM with per-bit trainable single-ended DFE and PLL-less clocking

2. 25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

3. A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process

4. 22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

5. A 7.5Gb/s/pi? LPDDR5 SDRAM with WCK Clocking and Non-Target ODT for High Speed and with DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power;ha;ISSCC,0

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5. A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces;IEEE Journal of Solid-State Circuits;2023-09