A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces-Reference-Cited by-同舟云学术

A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces

Published:2023-09 Issue:9 Volume:58 Page:2659-2667
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Jeong Yong-Un¹^ORCID,Chae Joo-Hyung²^ORCID,Kim Suhwan³^ORCID

Affiliation:

1. Department of Semiconductor Systems Engineering, Sejong University, Seoul, South Korea

2. Department of Electronics and Communications Engineering, Kwangwoon University, Seoul, South Korea

3. Department of Electrical and Computer Engineering, Seoul National University, Seoul, South Korea

Funder

Institute of Information and Communications Technology Planning and Evaluation

Ministry of Science and ICT

Faculty Research Fund of Sejong University in 2023

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10229945/10138801.pdf?arnumber=10138801

Reference28 articles.

1. A 16 Gb 9.5 Gb/S/pin LPDDR5X SDRAM with low-power schemes exploiting dynamic voltage-frequency scaling and offset-calibrated readout sense amplifiers in a fourth generation 10nm DRAM process;kim;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2022

2. A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

3. A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX

4. A 16 Gb sub-1 V 7.14 Gb/s/pin LPDDR5 SDRAM applying a mosaic architecture with a short-feedback 1-tap DFE, an FSS bus with low-level swing and an adaptively controlled body biasing in a 3rd-generation 10 nm DRAM;kim;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,2021

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1. A 56-Gb/s,0.708 pJ/bit single-ended simultaneous bidirectional transceiver with hybrid errors cancellation techniques for die-to-die interface;Microelectronics Journal;2024-10

2. A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02

3. A 56-Gb/S,0.708pj/Bit Single-Ended Simultaneous Bidirectional Transceiver with Hybrid Errors Cancellation Techniques for Die-to-Die Interface;2024