A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers
Author:
Affiliation:
1. School of Electronic Information and Electrical Engineering, Shanghai Jiao Tong University, Shanghai, China
Funder
National Key Technologies Research and Development Program of China
National Natural Science Foundation of China
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture
Link
http://xplorestaging.ieee.org/ielx7/8919/10416295/10325649.pdf?arnumber=10325649
Reference32 articles.
1. Recent Evolution in the DRAM Interface: Mile-Markers Along Memory Lane
2. A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process
3. 25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM
4. 22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process
5. 22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor
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