22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor-Reference-Cited by-同舟云学术

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22.4 A 32Gb/s Digital-Intensive Single-Ended PAM-4 Transceiver for High-Speed Memory Interfaces Featuring a 2-Tap Time-Based Decision Feedback Equalizer and an In-Situ Channel-Loss Monitor

Published:2020-02 Issue: Volume: Page:
ISSN:
Container-title:2020 IEEE International Solid- State Circuits Conference - (ISSCC)
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Author:

Chiu Po-Wei,Kim Chris

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/9046640/9062887/09063137.pdf?arnumber=9063137

Cited by 12 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 32 Gb/s Full duplex Bi-directional Transceiver with Crosstalk Cancellation for Chiplet Interconnections;2024 IEEE 74th Electronic Components and Technology Conference (ECTC);2024-05-28

2. A 0.83-pJ/b 20-Gb/s/Pin Single-Ended Transceiver With AC/DC-Coupled Pre-Emphasis FFE and Edge-Dependent Phase-Modulation DFE for Low-Power Memory Controllers;IEEE Transactions on Circuits and Systems I: Regular Papers;2024-02

3. A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces;IEEE Transactions on Circuits and Systems I: Regular Papers;2024

4. A 4-nm 16-Gb/s/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization;IEEE Journal of Solid-State Circuits;2024-01

5. A 56-Gb/S,0.708pj/Bit Single-Ended Simultaneous Bidirectional Transceiver with Hybrid Errors Cancellation Techniques for Die-to-Die Interface;2024

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