A 56-Gb/S,0.708pj/Bit Single-Ended Simultaneous Bidirectional Transceiver with Hybrid Errors Cancellation Techniques for Die-to-Die Interface
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Publisher
Elsevier BV
Reference23 articles.
1. Universal chiplet interconnect express (ucie): An open industry standard for innovations with chiplets at package level;D Das Sharma;IEEE Transactions on Components, Packaging and Manufacturing Technology,2022
2. A 0.90-tb/s/in 1.29-pj/b wireline transceiver with single-ended crosstalk cancellation coding scheme for highdensity interconnects;Q Liu;IEEE Journal of Solid-State Circuits,2023
3. A 4nm 32gb/s 8tb/s/mm die-to-die chiplet using nrz singleended transceiver with equalization schemes and training techniques;K Seong;2023 IEEE International Solid-State Circuits Conference (ISSCC),2023
4. A 0.85-pj/b 16-gb/s/pin singleended transmitter with integrated voltage modulation for low-power memory interfaces;Y.-U Jeong;IEEE Journal of Solid-State Circuits,2023
5. A 20-gb/s/pin compact single-ended dcc-less decs transceiver with cdr-less rx front-end for on-chip links;J Seo;IEEE Journal of Solid-State Circuits,2023
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