A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation-Reference-Cited by-同舟云学术

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation

Published:2022-01 Issue:1 Volume:57 Page:212-223
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Kang Ji-Hyo^ORCID,Yang Jaehyeok,Kim Kyunghoon,Chae Joo-Hyung^ORCID,Lee Gangsik,Byeon Sangyeon,Kim Boram,Kim Dong-Hyun,Kim Youngtaek^ORCID,Cho Yeongmuk,Ji Junghwan,Jeong Sera,Cha Jaehoon,Park Minsoo,Kim Hongdeuk,Park Sijun,Kim Sunho,Jung Hae-Kang,Jang Jieun^ORCID,Lee Sangkwon^ORCID,Kim Hyungsoo,Cho Joo-Hwan,Chun Junhyun,Cha Seonyong

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9664397/09559714.pdf?arnumber=9559714

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