13.9 A 25.2Gb/s/pin NRZ/PAM-3 Dual-Mode Transmitter with Embedded Partial DBI Achieving a 133% I/O Bandwidth/Pin Efficiency and 19.3% DBI Efficiency
Author:
Affiliation:
1. Kwangwoon University,Seoul,Korea
Funder
National Research Foundation
IC Design Education Center
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/10454133/10454267/10454326.pdf?arnumber=10454326
Reference6 articles.
1. A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation
2. A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ
3. An 8-Gb GDDR6X DRAM achieving 22Gb/s/pin with single-ended PAM-4 signaling;Hollis;JSSC,2022
4. A 0.64-pJ/Bit 28-Gb/s/Pin High-Linearity Single-Ended PAM-4 Transmitter With an Impedance-Matched Driver and Three-Point ZQ Calibration for Memory Interface
5. 23.3 A 3-bit/2UI 27Gb/s PAM-3 Single-Ended Transceiver Using One-Tap DFE for Next-Generation Memory Interface
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