A 7 ps Jitter 0.053 mm<formula formulatype="inline"> <tex Notation="TeX">$^{2}$</tex></formula> Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC-Reference-Cited by-同舟云学术

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A 7 ps Jitter 0.053 mm $^{2}$ Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC

Published:2009-09 Issue:9 Volume:44 Page:2437-2451
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Shin Dongsuk,Song Janghoon,Chae Hyunsoo,Kim Chulwoo

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx5/4/5226685/05226752.pdf?arnumber=5226752

Cited by 45 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A 65-nm duty-cycle corrector achieving 10% to 90% duty-correction range with <0.86% duty-cycle error;Microelectronics Journal;2024-08

2. A shared TDC-based fast-lock all-digital DLL using a DCC-embedded delay line;Microelectronics Journal;2024-07

3. A 65-Nm Duty-Cycle Corrector Achieving 10% to 90% Duty-Correction Range with < 0.86% Duty-Cycle Error;2024

4. A Shared Tdc-Based Fast-Lock All-Digital Dll Using a Dcc-Embedded Delay Line;2024

5. Design and Analysis of Asynchronous Sampling Duty Cycle Corrector;Electronics;2021-10-24

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