A 65-Nm Duty-Cycle Corrector Achieving 10% to 90% Duty-Correction Range with < 0.86% Duty-Cycle Error
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Publisher
Elsevier BV
Reference16 articles.
1. ps rms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOS;D Coombs;IEEE International Solid-State Circuits Conference (ISSCC),2017
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3. A stability-secured loop bandwidth controllable frequency synthesizer for multiband mobile DTV tuners;K.-W Kim;IEIE Transactions on Smart Processing & Computing,2015
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