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2. A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/s/pin 16Gb 4-H stack DDR4 SDRAM with TSVs;Yun,2015
3. A delay locked loop with a feedback edge combiner of duty-cycle corrector with a 20%–80% input duty cycle for SDRAMs;Lim;IEEE Transactions on Circuits and Systems II,2015
4. A fast-locking all-digital deskew buffer with duty-cycle correction;Chen;IEEE Transactions on VLSI Systems,2012
5. A 7ps jitter 0.053mm2 fast lock all-digital DLL with a wide range and high resolution DCC;Shin;IEEE J. Solid State Circ.,2009