A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-Voltage, Low-Power Applications-Reference-Cited by-同舟云学术

A Differential Flip-Flop With Static Contention-Free Characteristics in 28 nm for Low-Voltage, Low-Power Applications

Published:2023-05 Issue:5 Volume:58 Page:1496-1504
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Shin Gicheol¹^ORCID,Lee Eunyoung²,Lee Jongmin²^ORCID,Lee Yongmin²^ORCID,Lee Yoonmyung¹^ORCID

Affiliation:

1. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea

2. Memory Division, the Foundry Division, and the LSI Division, Samsung Electronics, Suwon, South Korea

Funder

Basic Science Research and Basic Research Laboratory Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Science and ICT

Samsung Electronics

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/10107667/09950607.pdf?arnumber=9950607

Reference20 articles.

1. Ultra-Low Power 18-Transistor Fully Static Contention-Free Single-Phase Clocked Flip-Flop in 65-nm CMOS

2. 27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications

3. A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving

4. A fully static topologically-compressed 21-transistor flip-flop with 75% power saving

5. A Static Contention-Free Differential Flip-Flop in 28nm for Low-Voltage, Low-Power Applications

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