1. S. Panda, S. Sharma, and A. R. Asati, “Clock gating analysis of TG based D flip-flop for different technology nodes,” in 2020 IEEE 7th Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), Prayagraj. IEEE, 2020, pp. 1–6.
2. Timing Analysis and Optimization Method with Interdependent Flip-Flop Timing Model for Near-Threshold Design
3. V. Mallaraddi, H. Rajani, and S. Kamate, “Static and dynamic power optimization using leakage feedback approach for nanoscale CMOS VLSI circuits,” in 2022 First International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT), Trichy. IEEE, 2022, pp. 1–5.
4. P. Parekh, F. Yuan, and Y. Zhou, “Area/power-efficient true-single-phase-clock D-flipflops with improved metastability,” in 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), Springfield, MA. IEEE, 2020, pp. 182–5.
5. K. D. Kumar, L. B. Reddy, V. Pudi, and S. Bodapati, “Design of low area and low power systolic serial parallel multiplier using CNTFETS,” in 2021 IEEE International Symposium on Smart Electronic Systems (iSES), Jaipur. IEEE, 2021, pp. 139–42.