Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability

Author:

Parekh Parth,Yuan Fei,Zhou Yushi

Publisher

IEEE

Cited by 10 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Implementation of High-Speed, Low-Power CMOS D Flip-Flop and Counters using Double Gate FinFET Technology;2024 5th International Conference for Emerging Technology (INCET);2024-05-24

2. Design and Analysis of Low-Power and Area-Efficient Master-Slave Flip-Flop;IETE Journal of Research;2024-05-21

3. Low-Voltage Flip-Flop Operation with Transition Completion Detection;2023 Global Conference on Information Technologies and Communications (GCITC);2023-12-01

4. Neoteric Design Power Sustained 3-Bit Asynchronous Counter Using CNFET Based MCML Topology;Advances in Electrical and Electronic Engineering;2022-10-03

5. Metastability Correction Techniques for TSPC-DFF with Applications in Vernier TDC;2022 IEEE International Symposium on Circuits and Systems (ISCAS);2022-05-28

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