Metastability Correction Techniques for TSPC-DFF with Applications in Vernier TDC
Author:
Affiliation:
1. Ryerson University,Department of Electrical, Computer, and Biomedical Engineering,Toronto,ON,Canada
Funder
Science and Engineering Research Council
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9937201/9937203/09937432.pdf?arnumber=9937432
Reference9 articles.
1. A 2.2-ps Two-Dimensional Gated-Vernier Time-to-Digital Converter With Digital Calibration
2. A High-Linearity, Ring-Oscillator-Based, Vernier Time-to-Digital Converter Utilizing Carry Chains in FPGAs
3. A Two-Channel Asynchronous SAR ADC With Metastable-Then-Set Algorithm
4. Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability
5. Background Calibration in Pipelined SAR ADCs Exploiting PVT-Tracking Metastability Detector
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