27.8 A static contention-free single-phase-clocked 24T flip-flop in 45nm for low-power applications
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Publisher
IEEE
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http://xplorestaging.ieee.org/ielx7/6747109/6757318/06757516.pdf?arnumber=6757516
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5. Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance Applications;IEEE Transactions on Emerging Topics in Computing;2023-10
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