CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop-Reference-Cited by-同舟云学术

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CMOS Clock-Gated Synchronous Up/Down Counter With High-Speed Local Clock Generation and Compact Toggle Flip-Flop

Published:2023-12 Issue:12 Volume:70 Page:5316-5327
ISSN:1549-8328
Container-title:IEEE Transactions on Circuits and Systems I: Regular Papers
language:
Short-container-title:IEEE Trans. Circuits Syst. I

Author:

Lee Geonhwi¹^ORCID,Joo Bomin²^ORCID,Kong Bai-Sun²^ORCID

Affiliation:

1. Department of Semiconductor Display Engineering, Sungkyunkwan University, Suwon-si, South Korea

2. Department of Electrical and Computer Engineering, Sungkyunkwan University, Suwon, South Korea

Funder

Samsung Electronics Co., Ltd. Design tools

IC Design Education Center

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture

Link

http://xplorestaging.ieee.org/ielx7/8919/10363413/10241984.pdf?arnumber=10241984

Reference37 articles.

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2. A Survey on the Edge Computing for the Internet of Things

3. Edge Computing: Vision and Challenges

4. A Survey on Internet of Things: Architecture, Enabling Technologies, Security and Privacy, and Applications

5. Performance Analysis of a Low-Power High-Speed Hybrid 1-bit Full Adder Circuit

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