A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68-Reference-Cited by-同舟云学术

A Sub-100 fs-Jitter 8.16-GHz Ring-Oscillator-Based Power-Gating Injection-Locked Clock Multiplier With the Multiplication Factor of 68

Published:2023-01 Issue:1 Volume:58 Page:78-89
ISSN:0018-9200
Container-title:IEEE Journal of Solid-State Circuits
language:
Short-container-title:IEEE J. Solid-State Circuits

Author:

Park Suneui¹^ORCID,Yoo Seyeon²^ORCID,Shin Yuhwan¹^ORCID,Lee Jeonghyun¹^ORCID,Choi Jaehyouk¹^ORCID

Affiliation:

1. School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea

2. Qualcomm Inc., San Diego, CA, USA

Funder

Samsung Electronics Company Ltd

National Research and Development Program through the National Research Foundation of Korea

Ministry of Science and Information and Communications Technology

Institute for Information & Communications Technology Promotion (IITP) Grant

Korea Government [Ministry of Science and Information and Communication Technology (MSIT)] (A Development of Intelligent Physical Layer (PHY) Interface for High-Speed Processing-in-Memory

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering

Link

http://xplorestaging.ieee.org/ielx7/4/9999561/09914018.pdf?arnumber=9914018

Reference32 articles.

1. A 0.0056-mm2 −249-dB-FoM All-Digital MDLL Using a Block-Sharing Offset-Free Frequency-Tracking Loop and Dual Multiplexed-Ring VCOs

2. Design of Crystal-Oscillator Frequency Quadrupler for Low-Jitter Clock Multipliers

3. Clock Multiplication Techniques Using Digital Multiplying Delay-Locked Loops

4. A Highly Digital MDLL-Based Clock Multiplier That Leverages a Self-Scrambling Time-to-Digital Converter to Achieve Subpicosecond Jitter Performance

5. 17.1 A ?240dB-FoMjitter and ?115dBc/Hz PN @ 100 kHz, 7.7GHz ring-DCO-based digital PLL using P/I-gain co-optimization and sequence-rearranged optimally spaced TDC for flicker-noise reduction;lee;IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers,0

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